A peripheral component interconnect (PCI) bus typically has multiple peripheral devices connected thereto. The peripheral devices use the PCI bus for communications within a computer system. As the operating frequency of the PCI bus increases, bus loading on the PCI bus limits a number of peripheral devices that be connected to the PCI bus at any given time while insuring uncorrupted data communications over the PCI bus. Because of such limitations, it is difficult and costly to implement computer systems, particularly servers, that generally need many peripheral devices on the PCI bus.
Previous efforts to solve this problem include the use of bus repeaters. A bus repeater uses logic to retransmit the signals of a primary, or master, PCI bus to a secondary, or slave, PCI bus. However, bus repeaters significantly reduce useable bus bandwidth and only support a limited subset of defined PCI bus operations. The logic necessary to implement the repeater function is rather complex and thus becomes a source of system unreliability. Moreover, a bus repeater necessarily adds another PCI bus to the computer system, increasing the complexity of the computer system. Therefore, it is desirable to have a capability to handle a large number of peripheral devices on a PCI bus despite the loading problems introduced by a multi-device implementation.